Semiconductor power devices, an example of which is shown in FIG. 1, typically include thousands of identical "active" cells, such as double-diffused metal-oxide-semiconductor (DMOS) transistors or insulated gate bipolar transistors (IGBT). These transistors are capable of controlling large voltages and currents at their cathode and anode terminals. The terminals of these devices are typically formed by a substrate, a polysilicon layer, and heavily-doped islands in the substrate, with a dielectric layer being present between the substrate and polysilicon layer to electrically insulate these structures from each other.
An IGBT 10 of a conventional IGBT power device is represented in FIG. 2. The IGBT 10 is formed in a substrate 12 to include a well 14 (e.g., a P-well), an island 16 (e.g., an N+ region within the P-well) beneath a hole formed in a polysilicon layer 18, and a metallization 20 overlying the polysilicon layer 18. The metallization 20 extends down through the hole to contact the island 16. When a positive voltage is applied to the polysilicon layer 18 (the gate terminal 28 of the IGBT 10), the surface of each well 14 is inverted, creating a channel through which electrons can laterally flow from the island 16 (the emitter/cathode region of the IGBT 10) to the substrate 12 and thereafter downward through the substrate 12 to a collector (anode) terminal 24.
An over-voltage (OV) clamp is generally required to protect the individual power devices of a semiconductor power device from experiencing avalanche breakdown. With continued reference to the IGBT power device of FIG. 2, which is schematically represented in FIG. 3, a string of polysilicon zener diodes 26 are shown as being connected between the collector (anode) terminal 24 and the gate terminal 28 of the IGBT 10 for this purpose. As shown in FIG. 2, the zener diode string 26 is typically formed in a section of the polysilicon layer 18 above a field oxide layer 22. As indicated by FIG. 3, the zener diode string 26 is located outside of the "active" area of the power device, i.e., that area of the substrate 12 in which the IGBT 10 is formed. A conventional arrangement can be seen from FIG. 1, in which a rectangular-shaped peripheral region 12a of the substrate 12 is allocated for the zener diode string 26, while the remainder of the substrate 12 forms an "active" region 12b of the substrate 12 for numerous IGBTs 10.
The breakdown voltage (BV) of the zener diode string 26 is designed to be less than the BV of the IGBTs 10. When the power device is "off," point "A" of a resistor 32, formed by a dielectric layer 30 (FIG. 2) separating the metallization 20 and the polysilicon layer 18, is "grounded" (i.e., connected to the emitter/cathode 16). If the anode voltage exceeds the BV of the zener diode string 26, current flows from the collector (anode) terminal 24 through the zener diode string 26 and the resistor 32 to the island (cathode) 16, causing a voltage to develop across the resistor 32. If this voltage exceeds the threshold voltage of the IGBT 10, the power device turns on and dissipates the energy present at the collector (anode) terminal 24, thereby protecting the IGBT 10 by preventing avalanche breakdown. Advantageously, the BV of the zener diode string 26 is much more stable over temperature and process variation than that of the IGBT 10, or any other bipolar or field-effect transistor (FET) device that may be employed in a power device of the type shown in FIG. 1.
The ruggedness of a semiconductor device is generally defined as the ability of the device to resist failure when its BV is exceeded. In order to increase the breakdown voltage and the ruggedness of a semiconductor power device, such as the IGBT of FIGS. 1 through 3, the active area 12b of the substrate 12 must be surrounded by an edge termination structure, such as that represented in FIG. 1 by the reference number 12c. An edge termination structure 12c of the type shown in FIG. 1 generally includes a continuous grounded well region, and possibly one or more floating well regions referred to as field-limiting rings (FLRs). These wells are generally formed by implants of the same impurity type as the wells of the power device, and completely encircle the power devices 10 within the active region 12b of the substrate 12. Because they are continuous, the grounded well region and the field-limiting rings serve to reduce the high electric fields that occur in the sharp corners of the substrate 12. As such, the presence of a grounded well region and one or more field-limiting rings enables a power device to sustain high voltages when in the "off" state. The effectiveness of an edge termination structure can be enhanced by using field plates that overlap the well of the edge termination structure. To achieve a BV of 600 volts, a power device may require one to three field-limiting rings, while six or more field-limiting rings may be required to attain a BV of 1200 volts.
While providing the above benefits, the design of an edge termination structure is complicated if a monolithic over-voltage clamp (e.g., the zener diode string 26 of FIGS. 2 and 3) is present in the "inactive" peripheral region 12a of the substrate 12, necessitating that the edge termination structure 12c be formed between the peripheral and active regions 12a and 12b, respectively, as shown in FIG. 1. As a result, prior art power devices have avoided continuous field-limiting rings, instead employing a single continuous grounded well or a series of polysilicon field plates. While being less complicated to fabricate, such power devices are generally limited to a BV of not more than 600 volts.
In view of the above, it would be desirable if a semiconductor power device were available that was configured to incorporate a monolithic over-voltage clamp and an edge termination structure that included a continuous grounded well and at least one field-limiting ring. Such a device would necessarily be uniquely configured to enable the presence of both the over-voltage clamp and the edge termination structure on the same substrate, yet preferably would be readily processed using known semiconductor processing techniques.